Chip Tape-Outs
High yield, field programmable flexible microprocessors (ISCA 2022)
Three distinct flexible microprocessor designs using Pragmatic’s 0.8 µm IGZO-TFT process. Each processor implements a distinct, custom instruction set designed to enable expressivity and low gate count microarchitectures.
| FlexiCore 8-bit | FlexiCore 4-bit with Extensions |
|---|---|
 |  |
Flexible Encryption Accelerators (Date 2023)
Three flexible encryption accelerators for ISO standard cryptosystems using Pragmatic’s 0.6 µm IGZO-TFT process. The AES-128 implementation is, to the best of my knowledge, the lowest gate count implementation of an AES-128 accelerator to be manufactured.
| AES-128 | PRESENT-128 | Simon |
|---|---|---|
 |  |  |
Organic Pseudo-CMOS microprocessor (Bring-up Pending)
RISC-V SoC 2022
An SoC consisting of a four-stage, single issue, in-order RISC-V core with split L1 caches, a high-throughput AES-128 accelerator, custom JTAG debug port, multiple SPI ports, external maskable and non-maskable interrupts, and 32 KiB integrated data memory in 65 nm silicon technology.
| Packaged Chip | Chip in testboard |
|---|---|
 |  |
OOO RISC-V Core 2023-2024
Design and tape-out of a performance oriented, dual-issue, out-of-order RISC-V core using explicit register renaming, and single-cycle misprediction recovery in Intel 16 nm technology. The 4 mm2 chip will be packaged with flip-chip packaging.